The present invention relates to semiconductor devices and manufacturing technology therefor and more particularly to semiconductor devices in which semiconductor chips originally designed for flip chip bonding are assembled by a wire bonding process.
Japanese Unexamined Patent Application Publication No. 2011-13502 describes a technique that a bonding wire for reference to supply a return current for a desired signal is located adjacently to a bonding wire to transmit the desired signal in order to reduce characteristic impedance mismatching in bonding wires and a substrate.
Japanese Unexamined Patent Application Publication No. 2010-278138 discloses a technique that reduces stress due to a thermal expansion coefficient difference, by sealing resin between a semiconductor chip and an interconnection substrate and a technique that equalizes the stress on the semiconductor chip by sealing resin placed all around the semiconductor chip.